Integrated automatic gain control (AGC), equalizer, filter and similar types of circuits can use an operational amplifier with resistance and capacitance in a feedback loop and a feed forward path to generate a desired transfer function. FIG. 1 illustrates a simple amplifier of the prior art in which the gain can be approximated by dividing the resistance in the feedback loop, R.sub.fb, by the resistance in the feed forward path, R.sub.ff. FIG. 2 depicts a simple gain stage in which the single feedback loop resistor, R.sub.fb, of FIG. 1 is replaced by a resistor network that can change the resistance in the feedback loop by manipulating switches s.sub.1 through s.sub.n. The gain or attenuation of the amplifier in FIG. 2 can be changed by switching combinations of feedback resistors in or out, thereby making an automatic gain control (AGC) circuit.
A problem with circuits like the one shown in FIG. 2 is that resistors in semiconductors are limited to diffusion or poly silicon resistors. It is well known that the abovementioned resistors have associated parasitic capacitances to the substrate. Parasitic capacitance adversely affects the performance of high speed circuits. The parasitic capacitance introduced into a circuit by each resistor can be modeled as a three terminal device with the third terminal usually being the substrate. The parasitic capacitance of integrated resistors can be modeled as shown in FIG. 3. FIG. 3 shows a symbol of a resistor with a desired value of resistance, R, and an undesired value of parasitic capacitance, C.sub.p, to the substrate.
The parasitic capacitance of the AGC circuit in FIG. 2 is included in the FIG. 4 model of the AGC circuit. In the model integrating parasitic capacitance, parasitic capacitor C.sub.p1 is added to the middle of feed forward resistor R.sub.1, which represents the feedforward resistor, R, from FIG. 2; and parasitic capacitor C.sub.p2 is added to the middle of feedback resistor R.sub.2, which represents the feedback loop resistor network, R.sub.1f through R.sub.nf, from FIG. 2. Ideally, the transfer function of the amplifier would be v.sub.o /v.sub.i =-R.sub.2 /R.sub.1. However, incorporating the parasitic capacitance results in the transfer function being represented by ##EQU1## where s represents the Laplace frequency component of the circuit. From equation 1, it is apparent that an unwanted zero and an unwanted pole are introduced to the system by the parasitic capacitances, as shown in equation 2. ##EQU2## As the gain increase, i.e., as R.sub.2 is increased, C.sub.P2 increases compared to C.sub.P1, causing the zero to become smaller compared to the pole. This results in unwanted peaking in the frequency domain and is depicted in FIG. 5.
Another source of parasitic capacitance in integrated circuits arises from the switches used in the circuit to adjust the amount of resistance in the feedback loop. The switches are generally NMOS transistors or composite NMOS and PMOS T-gates. The NMOS transistors and T-gates add capacitance to the circuit, due to a physical overlap between the drain-gate and the source-gate of integrated circuit transistors. Additionally, capacitance is added by reverse bias diodes which are used in NMOS and composite switches.
Another well-known approach used to create AGC circuits is shown in FIG. 6. The circuit in FIG. 6 allows the use of much smaller resistors in the feedback loop than the circuit depicted in FIG. 2 for equivalent levels of gain. This circuit uses a T-network resistor in the feedback loop instead of the single resistor path shown in FIG. 1. The gain for this circuit is approximated in the following equation: ##EQU3## This approach allows the use of smaller resistors in the feedback loop by using the 1/x relationship between the value of resistor R.sub.3 and the gain of the circuit in FIG. 6. The gain of the AGC can be changed by varying R.sub.3, with the gain increasing as the resistance of resistor R3 decreases. The T-network resistors, R.sub.2 and R.sub.3, shown in FIG. 6 can be much smaller that the feedback resistor R.sub.fb shown in FIG. 1 for a given amount of gain. However, there is a limit for lowering R.sub.2 and R.sub.3, since the maximum gain occurs when R.sub.3 is at a minimum. Therefore, an amplifier has to be able to drive a low resistor load equal to resistor R.sub.2 /2 plus resistor R.sub.2 /2 in parallel with resistor R.sub.3. This results in a tradeoff between lowering the feedback resistors and increasing the amplifier power to handle a low resistive load.
Assuming that the amplifier can drive a low resistive load, using resistors with low resistance for R.sub.2 and R.sub.3 and choosing to have the same number of resistance settings as the circuit shown in FIG. 2, the steps of the R.sub.3 resistor string must be very small. In order to keep the net transfer function accurate, the resistance of the switches has to be much smaller than each resistance step. This means that very large NMOS transistors or T-gates for switches are required, which results in additional parasitic capacitance. Also, because the gain varies with R.sub.3 as a function of 1/x as shown in FIG. 7, precision is lost as the resistance becomes very small due to small changes in resistance resulting in very large changes in gain.